TL;DR · 30-second read
The Short Version
The chips that run artificial intelligence are not held up by the factories that print them. They are held up by the assembly step at the end, where a processor and its memory are bonded onto a single slab so they can talk to each other fast enough.
Taiwan Semiconductor Manufacturing Company owns most of the world’s capacity for that step. Analysts in Taiwan say it plans to roughly double that capacity by 2028. Until it does, anyone building an artificial intelligence data center is standing in a queue. Intel is selling a rival method, and smaller assembly firms are absorbing the overflow.
Wccftech, citing a Taiwanese media report that quotes analysts, said TSMC plans to expand its chip-on-wafer-on-substrate (CoWoS) advanced packaging capacity to 260,000 wafers per month by the end of 2028, roughly double the approximately 130,000 wafers per month the same forecast puts it at by the end of 2026. The expansion is said to center on TSMC’s Arizona campus and its AP7 packaging facility in Taiwan.
The same forecast estimates that Intel’s competing EMIB-T packaging, converted into CoWoS-equivalent 12-inch wafer terms, could reach 15,000 to 20,000 wafers per month in 2027 and 40,000 to 45,000 in 2028, and says the CoWoS shortage has pushed work toward other packaging firms including Amkor, UMC and ASE. TSMC has not published a capacity target of its own. In a Form 6-K filed with the Securities and Exchange Commission on September 10, the company reported August 2026 consolidated revenue of NT$514.81 billion, up 53.3 percent from a year earlier.
Executive Summary
Advanced packaging is the step where a logic die and its stacks of high-bandwidth memory are mounted together onto a shared substrate so they behave as one component. CoWoS is TSMC’s version, and it is the packaging used for the accelerators that fill AI data centers. For roughly three years it, rather than leading-edge wafer manufacturing, has been the narrowest point in the supply chain for those parts.
A doubling of that capacity by 2028 would be the single largest change to AI hardware availability that any one company can make. It would not, however, double accelerator output in a straight line. Package sizes are growing, the newest designs consume more interposer area and more memory stacks per unit, and a wafer of packaging substrate therefore yields fewer finished accelerators each generation than it did the year before. Capacity that doubles against demand that also rises per unit is not the same as supply that doubles.
TSMC’s own disclosure does not address packaging capacity. What its September 10 filing does show is demand running hot: August revenue rose 53.3 percent year over year, and revenue for the first eight months of 2026 was up 39.3 percent. That is consistent with a company selling everything it can finish, which is the condition under which a capacity forecast of this kind becomes credible without being confirmed.
The Bottleneck Moved Downstream
For most of the history of the chip industry, the scarce resource was the front end: photolithography tools, leading-edge wafer starts, yield on a new process node. Packaging was the cheap, unglamorous back end. AI accelerators inverted that. A modern accelerator is not one chip but an assembly, a large logic die surrounded by stacks of memory, all sitting on a silicon interposer threaded with vertical connections called through-silicon vias. The density of those connections is what delivers the memory bandwidth the workload needs. That assembly step is CoWoS, and there is no abundant substitute for it.
The practical consequence for anyone financing a data center is that wafer capacity is no longer the number to watch. A foundry can start more wafers than it can finish into packages, and unfinished silicon does not train models. The forecast of 130,000 wafers per month at the end of 2026 rising to 260,000 by the end of 2028 is, in effect, a two-year schedule for how quickly the industry can convert build-ready halls into loaded racks.
Read it with care, though. Interposer area per accelerator has been climbing with every generation as designers add memory stacks and reticle-stitched logic. If the average package consumes meaningfully more of a wafer in 2028 than it does today, unit output grows by considerably less than the wafer count suggests. Doubling the input is a ceiling on supply growth, not a promise of it.
Arizona Can Print the Chips but Cannot Finish Them
The most operationally interesting detail in the forecast is geographic. Wafers produced at TSMC’s Arizona campus are flown to Taiwan to be packaged, because the packaging capacity sits on the island. Siting part of the expansion in Arizona alongside the AP7 facility in Taiwan would begin to close that loop, turning an American fab from a wafer source into something closer to a finished-component source.
That matters for reasons beyond logistics. A round trip across the Pacific adds days of cycle time and a customs and freight cost to every high-value wafer, and it means that the resilience argument for building fabs outside Taiwan is currently incomplete. A domestic fab whose output must still transit Taiwan to become a usable product does not remove the concentration risk that justified it. TSMC’s own filing shows the Arizona entity is treated as a significant subsidiary, with parent guarantees extended to TSMC Arizona among other affiliates, but the filing says nothing about packaging there.
For data center operators and the governments underwriting them, this is the question worth asking of any onshoring announcement: does the site produce a wafer or a shippable part? Until packaging follows fabrication, the answer for Arizona remains the former.
Intel’s EMIB-T and the Value of a Second Source
Intel’s EMIB-T takes a different architectural route. Instead of building the whole assembly on a large silicon interposer, it embeds small silicon bridges inside the organic substrate and places the logic and memory dies on top. Less silicon is used, which can mean lower cost and fewer of the handling and warpage problems that come with very large interposers, but the approach historically trades away some of the interconnect density that the largest, most bandwidth-hungry designs demand.
The forecast puts EMIB-T at 40,000 to 45,000 CoWoS-equivalent wafers per month by 2028. Against 260,000, that is a meaningful second source rather than a competitive threat, on the order of a sixth of the leader’s volume. The claim that it suits custom accelerators of the kind Google and Amazon design is plausible on architecture, since in-house cloud silicon is generally tuned for a known workload and a known cost target rather than for maximum bandwidth per package. It is also unverified: neither Intel nor any cloud provider has announced such an arrangement.
The spillover to Amkor, UMC and ASE follows the same logic. When the preferred supplier is sold out, work migrates to whoever can perform an adjacent version of it, and outsourced assembly and test firms have been the natural landing place. Buyers get optionality and a check on pricing. The risk is that second-source packaging is not a drop-in substitute. Requalifying a part on a different packaging architecture is an engineering program, not a purchase order, and the customers best placed to do it are the ones designing their own silicon.
What Is Substantiated and What Is Not
The demand side of this story rests on disclosed figures. TSMC’s September 10 filing with the Securities and Exchange Commission reports August consolidated revenue of NT$514.81 billion, a 10.1 percent increase on July and 53.3 percent on August 2025, with the first eight months of 2026 up 39.3 percent year over year. Growth at that rate at TSMC’s scale is difficult to explain without sustained AI accelerator demand behind it.
The supply side is a forecast, not a commitment. The 260,000 figure, the 130,000 baseline, the Arizona and AP7 split and the EMIB-T range all come from analysts rather than from the companies. None of the three firms named has published a packaging capacity target, a capital budget attached to one, or a schedule. Analyst capacity models in this industry have a reasonable track record on direction and a poorer one on timing, because packaging expansions depend on tool delivery, cleanroom construction and qualification cycles that slip quietly.
The sober reading is that the direction is well supported and the magnitude is an estimate. Treat 2028 as the earliest plausible date for materially looser accelerator supply, treat the doubling as a ceiling rather than a plan of record, and treat any procurement model that assumes it as carrying schedule risk that TSMC has not underwritten.
Background
TSMC is the world’s largest contract chip manufacturer, building processors designed by other companies. It commercialised CoWoS in the 2010s as a niche technique for high-performance parts, long before AI accelerators turned it into the scarcest resource in the industry. Today the packaging step determines how many finished accelerators reach the market, because a logic die without its memory bonded alongside it is not a usable product.
The competitive response has come from two directions. Intel has pushed its own bridge-based packaging as part of its foundry ambitions, targeting customers who want a supplier outside Taiwan or a lower-cost assembly for custom silicon. Outsourced assembly and test firms such as Amkor, ASE and UMC have absorbed work that TSMC cannot schedule. None of this has yet changed the basic shape of the market, in which one company’s packaging line sets the pace at which AI data centers can be filled. Source: Report: TSMC to Double CoWoS Capacity by 2028 as AI Chip Shortage Spills Over to Rivals, which relays a Taiwanese analyst forecast for TSMC’s advanced packaging capacity and for Intel’s competing EMIB-T volumes. Primary sources: Taiwan Semiconductor Manufacturing Company, Form 6-K filed September 10, 2026 (August 2026 revenue report), filed with the US Securities and Exchange Commission.Sources