TL;DR · 30-second read
The Short Version
The chips behind artificial intelligence are not just manufactured. They are also assembled, with several chips and stacks of memory joined into one module. That assembly step has become a choke point.
Taiwan Semiconductor Manufacturing Company is reportedly discussing raising its price for this assembly by up to a fifth. Its customers have few alternatives, and a new assembly plant takes about three years to reach full speed.
If the increase goes ahead, the bill flows to the companies building the computers that run artificial intelligence services.
China Times reported, citing supply chain sources, that Taiwan Semiconductor Manufacturing Company (NYSE: TSM) is discussing a price increase of up to 20% for its CoWoS advanced packaging. The report says demand for AI GPUs and custom ASICs is outpacing supply and some lead times have already lengthened. TSMC has not confirmed the report.
According to the same report, TSMC is raising CoWoS capacity to 130,000 wafers a month in 2026 and targeting 200,000 in 2027, with a U.S. plant expected to start production in 2028. Packaging equipment lead times have stretched from three to six months to six to eight months.
Executive Summary
TSMC is reportedly discussing a price increase of up to 20% for CoWoS. CoWoS is the advanced packaging process that joins compute dies and high-bandwidth memory into the single modules that power AI GPUs and custom ASICs. The cause is a mismatch the company cannot close quickly. Demand keeps outrunning supply, and new packaging capacity takes years, not months, to reach full output.
The significance goes beyond one supplier’s margins. Packaging now limits how many AI accelerators reach the market, and as packages grow larger, each one uses more equipment time. If the increase goes through, chip designers will either absorb the cost or pass it into AI server prices. It would also show that the assembly step, and not only chip fabrication, now carries pricing leverage in the AI hardware supply chain.
Why the Packaging Step Can Set Its Own Price
Pricing power comes from scarcity without substitutes, and CoWoS currently has both. Demand from AI accelerator designers continues to outpace supply. Lead times have already lengthened, and the increase under discussion would be another round on top of earlier ones. A supplier that is sold out and has raised prices before is well placed to raise them again.
Supply cannot respond quickly. Industry sources say a new advanced packaging facility takes roughly three years to reach full load at its bottleneck stations, because construction and tool installation must be followed by calibration and validation. Equipment lead times have stretched from three to six months to six to eight months, as toolmakers’ own component suppliers run at capacity. TSMC is reportedly lifting CoWoS output to 130,000 wafers a month in 2026 and targeting 200,000 in 2027, with a U.S. plant expected to start production in 2028. Each of those additions arrives on a construction-and-qualification schedule, not as fast as orders come in.
Switching to another supplier is just as slow. The leading GPU and custom ASIC designers have built their design tools, HBM memory partnerships and test flows around CoWoS, which makes it the lowest-risk route to market. Moving a flagship accelerator to different packaging means requalifying all of that. This is why customers are expected to accept an increase of up to 20% rather than gamble on an alternative. For a buyer whose product launch depends on securing packaging slots, the price of a slot matters less than having one.
Bigger AI Chips Use Up Capacity Faster
A less obvious driver is physical size. Each new generation of AI accelerator puts more compute dies and more HBM stacks into a single package. HBM, or high-bandwidth memory, is memory stacked vertically and placed right beside the processor. Larger packages are harder to build, and they reduce the hourly output of packaging equipment. A customer shipping the same number of chips this year as last year can therefore need more tools to do it.
That changes how capacity figures should be read. A target expressed in wafers per month does not convert into accelerators at a fixed rate, because fewer large packages fit on each wafer. TSMC says its 5x-reticle packages are already in volume production with strong yields. A reticle is the maximum area a lithography tool can print in one exposure. Versions at 9x and 14x are in development. Each step up widens the gap between headline capacity growth and the number of finished accelerators it supports.
Testing adds to the pressure. AI processors take longer to test, so packaging and test capacity are now strained at the same time. A bottleneck that spans two consecutive steps is harder to clear, because adding capacity at one step mainly moves the queue to the next.
Where the Bill Lands
Packaging is billed to the chip designer, but the designer is rarely the final payer. GPU vendors and custom ASIC developers sell into AI server builds. A higher packaging cost either reduces their margins or raises accelerator prices, and from there it reaches the capital budgets of cloud providers and data center operators. How much of a 20% packaging increase shows up in the price of a finished server depends on packaging’s share of an accelerator’s total cost. None of the parties has disclosed that share.
For infrastructure planners, timing may matter more than price. When packaging slots are the constrained input, accelerator delivery schedules depend partly on a packaging ramp measured in years. Those schedules in turn decide when powered and cooled data center halls actually fill with equipment. Buyers with secured allocations are protected. Those buying on shorter notice face both higher prices and longer waits.
Is EMIB a Real Alternative?
Intel’s EMIB connects chips with small silicon bridges embedded in an organic substrate, rather than a full silicon interposer. It uses less silicon and works well for moderate interconnect needs. Its supporters present it as a second source when CoWoS is sold out. It is generally considered harder to scale for very large, HBM-heavy designs, which are exactly the parts driving CoWoS demand.
A fair reading is that CoWoS’s lead reflects ecosystem maturity and timing as much as technical merit. A sustained price premium gives customers a reason to qualify a second source over time. TSMC is also developing its own lower-cost route, panel-based CoPoS, aimed at larger packages at lower cost. An increase of up to 20% could strengthen TSMC’s near-term margins while also strengthening the case for alternatives in the next chip design cycle.
Background
TSMC, headquartered in Hsinchu Science Park, Taiwan, and listed in New York as TSM, is a contract chipmaker that manufactures chips other companies design. As AI accelerators grew larger and needed more memory, the industry shifted to advanced packaging, which combines several compute dies and stacks of HBM in one module. TSMC’s CoWoS does this with a full silicon interposer that supports extremely dense connections. It has become the platform the leading GPU and custom ASIC designers build around.
Intel’s EMIB, which embeds small silicon bridges in an organic substrate, is the most commonly cited alternative. TSMC is developing larger CoWoS packages at 9x and 14x reticle size, beyond the 5x already in volume production. It is also developing panel-based CoPoS, aimed at larger packages at lower cost. Source: Demand & Complexities Of AI GPUs And Custom ASICs Have Stressed TSMC’s CoWoS Supply, Reportedly Sparking The Possibility Of A 20% Price Hike (Wccftech): citing China Times, reports that TSMC is weighing an increase of up to 20% for CoWoS advanced packaging. Also covered by Yahoo Finance and Investing.com. Primary sources: Taiwan Semiconductor Manufacturing Company, Form 6-K filed 2026-10-22 (SEC EDGAR).Sources